The present application relates to semiconductor device manufacturing, and more particularly to a method of forming a deep trench isolation structure in a semiconductor material portion of a semiconductor substrate and thereafter epitaxially growing semiconductor fins on selected areas of a topmost surface of the semiconductor substrate.
The use of non-planar semiconductor devices such as, for example, finFETs, trigate and gate-all around semiconductor nanowire field effect transistors (FETs) is the next step in the evolution of complementary metal oxide semiconductor (CMOS) devices. Current process flow for trench isolation structure formation for future technology nodes including, finFETs, are restricted by the fundamental limits of the lithographic process. Moreover, current process flows are further restricted by semiconductor fin and trench isolation structure tapering through reactive ion etching since prior art processes cut the semiconductor fin after it is already formed in a semiconductor material.
In view of the above, a process is needed that seeks to remove the taper component variation impact on technology process assumptions.